Non-volatile memory, in which there is no loss of stored data even in the event of a power supply interruption, is widely used for data storage in a variety of devices, including, for example, digital cameras and mobile phones. FIG. 1 illustrates a prior art single-transistor stacked cell structure for realizing a non-volatile memory device.
As shown in FIG. 1, a single-transistor stacked cell includes a semiconductor substrate 11; a tunnel oxide layer 12 selectively formed on a predetermined area of the semiconductor substrate 11; a stacked gate structure composed of a floating gate 13, an intergate insulating layer 14, and a control gate 15; an insulating layer spacer 16 disposed on either side of the stacked gate structure; an insulating layer 17 formed between the stacked gate structure and the insulating layer spacer 16; lightly doped drains 18a and 18b formed in the surface of the semiconductor substrate substantially under the insulating layer spacer 16; source/drain junctions 19a and 19b formed in the surface of the semiconductor substrate substantially beyond either side of the insulating layer spacer 16; and a silicide layer 20 formed on the source/drain junctions and on the control gate atop the stacked gate structure.
A single-transistor stacked cell constituted as described above enjoys a small footprint to facilitate device integration. In such a stacked cell, the floating gate 13 is fully enclosed by a dielectric layer and serves as the charge storage unit of the cell. In programming such a cell, hot-electron channel injection is applied to inject electrons into the floating gate 13 and to, thus, raise its threshold voltage (VT). In an erase operation electrons are removed from the floating gate 13 via Fowler-Nordheim (FN) tunneling to lower the threshold voltage (VT).
An over-erase state (i.e., VT≦0V) may occur due to a non-uniformity in semiconductor fabrication, (particularly, due to a non-uniformity in the thickness of the tunnel oxide layer 12), or due to stress being applied to the dielectric layer enclosing the floating gate 13. Here, it should be noted that none of the cells of a given bit line can be read if over erasing occurs in any one of the cells. Therefore, the prevention of over-erasing is a crucial operational requirement. Generally, in a single-transistor stacked cell such as that of FIG. 1, the problem of over-erasing is overcome by detecting over-erased cells and programming the detected cells after increasing their threshold voltages. This process, however, consumes excessive test time, requires a complicated circuit to compensate for the threshold voltages of the over-erased cells, and increases the complexity of the data-erasing process. Furthermore, to address the over-erasing problem, the single-transistor stacked cell is configured to prevent occurrence of the over-erasing state altogether, namely, by narrowing the range (window) of the allowable threshold voltage of the cell. In this regard, when performing the erasing operation in block units of more than several tens of kilobytes, a statistical threshold voltage distribution of an erased block is over-extended, thereby reducing an actual allowable threshold voltage range.
In the above-described non-volatile memory cell, a charge state of the floating gate (i.e., a threshold voltage) corresponds to a memory logic state. For an input voltage of 3.3V, the allowable threshold voltage range of the single-transistor stacked cell is about 1.0V˜5.0V, and the cell current flowing in the single-transistor stacked cell is determined accordingly. For example, if a read voltage of 3.3V is applied to a control gate having a low-level threshold voltage set to 1.0V, the cell current corresponds to the difference (i.e., 3.3V−1.0V). On the other hand, when applying a read voltage of 3.3 V to a cell programmed at 5.0V, the current path in the channel of the cell is blocked. Thus, in a single-transistor stacked cell, when a read voltage is applied, either a current-flowing state or a current-blocking state is detected. These two current states correspond to two logic level states (i.e., a logic “1” and a logic “0”), thereby enabling the storage of one bit of digital data per cell.
In a data read operation, the data read speed of the memory is directly proportional to the cell current. That is, high cell current means high data read speed and vice versa. Therefore, since lower threshold voltages enable higher cell currents, a lower threshold voltage also means a higher read speed. Due to its low cell current, the above-described single-transistor stacked cell has difficulty in improving the data read speed.
Attempts to achieve a further reduced cell size (increased fineness) to meet the specification rule of the single-transistor stacked cell also have negative effects (e.g., poorer cell characteristics and lower cell reliability). For example, in the single-transistor stacked cell arranged in a memory array, a drain is directly connected to a bit line, and a source is connected to a common ground line. As such, when a drain voltage is applied, a drain turn-on or block-transistor punchthrough phenomenon occurs and high leakage current is generated due to the drain's coupling to the floating gate. Therefore, a program current is increased, so that the number of charge pumping circuits must be increased. The drain turn-on, punchthrough, and high leakage current effects are amplified in inverse proportion to the width of the channel. Consequently, it is difficult to reduce the cell size. In addition, the memory array may unexpectedly inject hot electrons into non-selected cells contained in a selected bit line due to the leakage current. Further, the memory array may encounter a charge leakage problem in the non-selected cells due to electric field stress. In addition, a deterioration of a neighboring oxide layer of the floating gate of the storage transistor (cell) may occur when a contact and wiring process is performed with respect to the drain.
Even with the development of microfabrication technology, and although a flash memory cell may have a single-transistor structure, it is still difficult to reduce cell size due to the several problems described above. To solve these problems, the single-transistor stacked cell may include a selection gate transistor connected in series to the floating gate transistor. However, inclusion of such a selection gate transistor requires an allotment of an additional area during cell integration, which counteracts efforts to reduce cell size.
Wherever possible, like reference numbers are used throughout the drawings to refer to the same or similar parts.